Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design
Job Description
Microsoft Quantum has assembled a talented and diverse international team to create the world's first scalable quantum computing system. Our full-stack approach involves exciting innovations from physics on the quantum plane to providing global quantum services. The Microsoft Quantum program strives to fundamentally change the world of computing to help solve humankind's currently unsolvable problems.
This role involves deep, technical work in a small, collaborative environment, focusing on the development of essential building blocks in the control and readout chain of quantum hardware implementations. The successful candidate will contribute to the architecture, specification, design, test, and development of CryoCMOS functions and ASICs to support full-stack quantum hardware implementations.
Key responsibilities include:
- RTL design and implementation from specification to GDS
- Verification environment development using UVM
- Cryogenic and room temperature measurements of ASICs
- Collaboration with analog, architecture, and cryogenics teams
- Implementation of lab safety protocols and best practices
The position offers competitive compensation ($119,800 - $234,700 base pay range, higher in SF Bay Area and NYC: $158,400 - $258,000) and comprehensive benefits including healthcare, educational resources, savings plans, and parental leave.
The ideal candidate will have extensive experience in digital logic design, ASIC development, and deep sub-micron technologies. Knowledge of quantum physics and cryogenic circuit design is highly desirable. This is an opportunity to have a meaningful influence on revolutionary technology while working with a diverse staff of theoretical and experimental physicists, hardware designers, and software engineers worldwide.
Responsibilities For Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design
- Contribute to architecture, specification, design, test, and development of CryoCMOS functions and ASICs
- Implement RTL to GDS in Physical Design domain
- Define and implement UVM-based verification environments
- Conduct cryogenic and room temperature measurements of ASICs
- Collaborate with analog, architecture, and cryogenics teams
- Use lab best practices and protocols
- Ensure hazards and risks are identified and controlled
- Work in accordance with health and safety policies
Requirements For Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years experience
- Experience in digital logic design including microarchitecture specification development
- RTL coding in Verilog/System Verilog
- Experience with design verification, CDC/Lint closure synthesis
- Knowledge of floorplanning, place and route, timing constraint, and post-silicon debug
- Deep experience with EDA software for digital design (Cadence suite)
- Effective team collaboration and communication skills
- Experience with report writing and documentation
Benefits For Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
Related Jobs
