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ASIC Verification Engineer

NVIDIA is the world leader in accelerated computing, pioneering solutions for challenges no one else can solve.
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Mid-Level Software Engineer
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5,000+ Employees
3+ years of experience
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Description For ASIC Verification Engineer

NVIDIA, a pioneer in GPU technology and AI innovation, is seeking an ASIC Verification Engineer to join their team in Hyderabad, India. This role is crucial in implementing cutting-edge verification methodologies for Design-for-Test (DFT) IP at unit and system levels.

As an ASIC Verification Engineer, you will:

  • Build state-of-the-art verification test benches for complex IPs, sub-systems, and SOCs
  • Develop and own verification environments using UVM or equivalent
  • Create reusable bus functional models, monitors, checkers, and scoreboards
  • Drive functional coverage-driven verification closure and own design verification sign-offs
  • Collaborate with multi-functional teams including chip architecture, ASIC design, functional verification, and post-silicon teams
  • Contribute to innovation in improving DFT methods

The ideal candidate will have:

  • BSEE with 3+ or MSEE with 2+ years of experience in DFT verification or related domains
  • Expertise in SystemVerilog and UVM/VMM verification methodologies
  • Proficiency with prototyping, verification, and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime, etc.)
  • Strong programming skills in C++, Perl, Python, or Tcl
  • Excellent communication skills and problem-solving abilities

Additional valuable skills include:

  • Experience in both DFT and RTL Verification domains
  • Knowledge of Formal verification methodologies
  • Hands-on experience in post-silicon debug on ATE and/or system labs

Join NVIDIA in their mission to amplify human imagination and intelligence through groundbreaking innovations in GPU technology, AI, and accelerated computing.

Last updated 9 months ago

Responsibilities For ASIC Verification Engineer

  • Build state of the art verification test benches for complex IPs/Sub-systems/SOCs
  • Develop and own verification environment using UVM or equivalent
  • Build reusable bus functional models, monitors, checkers and scoreboards
  • Own functional coverage driven verification closure and design verification sign-offs
  • Collaborate with multi-functional teams (chip architecture, ASIC design, functional verification, post silicon)
  • Contribute to innovation in improving DFT methods

Requirements For ASIC Verification Engineer

Java
Python
  • BSEE with 3+ or MSEE with 2+ years of experience in DFT verification or related domains
  • Expertise in System Verilog and verification methodologies like UVM/VMM
  • Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc)
  • Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures
  • Strong programming/scripting skills in C++, Perl, Python or Tcl
  • Excellent written and oral communication skills
  • Strong analytical and problem solving skills

Interested in this job?