Lead Layout Mask Design Engineer
Job Description
NVIDIA, a global leader in accelerated computing and AI technology, is seeking a Lead Layout Mask Design Engineer to join their Digital IP Team. This role represents an exciting opportunity to work at the forefront of semiconductor design, focusing on next-generation custom SRAM development.
The position involves working with cutting-edge process technology that will be implemented across NVIDIA's product line. As a lead engineer, you'll be responsible for performing physical layout for custom embedded SRAM structures using advanced sub-micron CMOS technologies and Cadence tools. The role combines technical expertise with leadership, requiring you to guide and influence other layout designers while improving team efficiency.
NVIDIA's environment is perfect for those passionate about pushing technological boundaries. The company has a rich history of innovation, from inventing the GPU in 1999 to revolutionizing AI through GPU deep learning. They offer competitive compensation, with base salaries ranging from $124,000 to $230,000 depending on level and experience, plus equity and comprehensive benefits.
The ideal candidate brings 8+ years of proven experience in mask and layout design, deep understanding of circuit layout concepts, and expertise with Cadence tools. You'll need strong technical skills in verification tools and debugging, combined with excellent communication and leadership abilities. Experience with SRAM design and compiler work is highly valued.
This hybrid position is based in Santa Clara, CA, putting you at the heart of NVIDIA's innovation center. You'll be part of a team that's driving the future of computing technology, working on projects that impact NVIDIA's entire product ecosystem. The role offers the perfect blend of technical challenges and leadership opportunities, making it ideal for experienced professionals looking to advance their careers in semiconductor design.
Responsibilities For Lead Layout Mask Design Engineer
- Perform physical layout for custom embedded SRAM structures in state-of-the-art sub-micron CMOS technologies using Cadence tools
- Assist in floor planning, custom layout and verifying against design rules and schematics
- Perform power robustness check and EMIR verification and fixes
- Negotiation with P&R on setting up ram interface spec
- Lead and influence other layout designers to improve team efficiency and align design methodology
Requirements For Lead Layout Mask Design Engineer
- Associates degree (or equivalent experience)
- 8+ years proven experience in mask and layout design
- Deep understanding of digital and analog circuit layout concepts in submicron CMOS technologies
- Strong background with Cadence custom circuit design tools - particularly Virtuoso
- Experience running and debugging with verification tools such as ICV or Calibre
- Knowledge of DRC and LVS checking flows, ability to customize decks
- Strong communication skills
- Prior management experience preferred
- Can effectively work in a team, good interpersonal skills
- SRAM digital custom block design experience (preferred)
- SRAM compiler experience (preferred)
Benefits For Lead Layout Mask Design Engineer
- Competitive salaries
- Generous benefits package
- Equity
Related Jobs
