Taro Logo

Manager, Design-for-Test - ATPG

World leader in accelerated computing, pioneering AI and digital twins technology.
Embedded
Staff Software Engineer
In-Person
5+ years of experience
AI · Hardware
This job posting may no longer be active. You may be interested in these related jobs instead:

Description For Manager, Design-for-Test - ATPG

NVIDIA, the world leader in accelerated computing, is seeking an experienced Design-for-Test (DFT) Engineering Manager to join their ATPG team. This role offers an exciting opportunity to work on groundbreaking innovations in hardware technology, leading a team of 10-15 engineers in developing next-generation DFT technologies.

The position involves managing critical aspects of semiconductor chip testing and validation, working with some of the most sophisticated semiconductor chips in the industry. You'll be responsible for coordinating multiple projects simultaneously while collaborating across various teams including chip design, backend, verification, and production testing.

The role requires strong technical expertise in DFT/ATPG, including knowledge of scan, BIST, on-chip scan compression, fault models, and fault simulation. You'll be working with cutting-edge technologies and complex products, where DFT solutions are uniquely developed in-house and continuously evolved to meet challenging goals.

NVIDIA offers an exciting and educational environment where individual contributions significantly impact product development and achievements. The company is known for being one of the technology world's most desirable employers, working on revolutionary products that transform industries through AI and digital twins technology.

This is an excellent opportunity for someone who combines technical expertise with leadership skills and wants to be at the forefront of semiconductor innovation. You'll be part of a team that creates solutions for the industry's most complex challenges while leading and developing a talented engineering team.

Last updated 8 months ago

Responsibilities For Manager, Design-for-Test - ATPG

  • Managing a team of 10-15 ATPG/scan insertion/DFT Post Si Engineers
  • Leading the development of next generation DFT technologies
  • Coordinate multi projects execution in parallel
  • Leading automation flows and processes for short test time to production
  • Working closely with chip design, backend, verification, and production testing teams

Requirements For Manager, Design-for-Test - ATPG

  • 2+ years of proven management experience and skills in the DFT field
  • 5+ overall years of hands-on DFT/ATPG experience
  • BSc. in Electrical Engineering or Computer engineering
  • Quick learner, proactive and self-motivated
  • Knowledge of DFT/ATPG including scan, BIST, on-chip scan compression
  • Experience in Mentor TestKompress ATPG tool and retargeting flow

Interested in this job?