Senior ASIC Verification Engineer
Job Description
NVIDIA, the world leader in accelerated computing, is seeking a Senior ASIC Verification Engineer to join their innovative team. This role offers a unique opportunity to work on cutting-edge technology that spans from consumer graphics to self-driving cars and artificial intelligence. The position involves applying advanced formal methodologies to verify complex digital designs, IP blocks, and SoCs, making a direct impact on NVIDIA's groundbreaking products.
As a Senior ASIC Verification Engineer, you'll be responsible for developing and implementing robust test plans, working closely with design teams, and ensuring verification closure. The role requires expertise in hardware description languages like Verilog/System Verilog, strong analytical skills, and a deep understanding of verification methodologies.
NVIDIA's work environment is characterized by passionate professionals united in their quest to transform the way graphics and parallel computing are used to solve complex problems. The company has evolved from creating gaming and entertainment graphics to developing AI technologies that power intelligent machines and breakthrough innovations.
This is an excellent opportunity for experienced verification engineers who want to be part of a global team pushing the boundaries of technology. The position offers the chance to work on diverse projects that have real-world impact, from advancing gaming technology to enabling autonomous vehicles and artificial intelligence applications.
Responsibilities For Senior ASIC Verification Engineer
- Apply best-in-class formal methodologies to verify complex digital designs, IP blocks and SoCs
- Take ownership of verifying designs by developing robust test plans
- Implement test plans by working with the design team
- Coordinate with other verification team members for closure
Requirements For Senior ASIC Verification Engineer
- B.Tech./ M.Tech. with 5+ years of relevant experience
- Strong analytical skills to solve difficult problems
- Understanding of abstraction techniques for effective verification
- Hands-on experience with HDLs such as Verilog / System Verilog
- Ability to quickly understand RTL design
- Understanding of temporal logic assertions
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