ASIC Timing and Methodology Engineer

Qualcomm Technologies, Inc. is seeking an experienced ASIC Timing and Methodology Engineer to join their engineering team in San Diego. This role offers an exciting opportunity to work on cutting-edge semiconductor technology for mobile, compute, automotive, and IoT markets.

The position involves working with state-of-the-art methodologies and tools in advanced process nodes (5nm, 4nm and beyond). As a Timing Engineer, you'll be responsible for crucial timing analysis and methodology development, working closely with physical design teams, CAD teams, and IP teams to ensure successful timing closure and sign-off for complex SOCs.

The role requires expertise in various industry-standard tools and technologies, including Spice simulations, PT/PT-SI, Tempus, and timing ECO tools. You'll be contributing to improving timing convergence processes across the company, enhancing design PPA, yield, and supporting new advanced process technologies from PDK to VLSI design production.

Qualcomm offers a competitive compensation package, including a base salary range of $140,000 to $210,000, plus annual bonuses and RSU grants. The company provides comprehensive benefits including medical coverage, 401k, and various other perks to support work-life balance.

This is an excellent opportunity for experienced professionals who want to work at the forefront of semiconductor technology with one of the industry's leading companies. The role combines technical expertise with strategic thinking, offering significant impact on next-generation semiconductor products.

The ideal candidate will have strong programming skills in Python, Perl, TCL, and Unix shell, along with a deep understanding of digital design flows and timing analysis. Experience with machine learning modeling is considered a plus. The position requires at least 4 years of relevant experience, along with a bachelor's degree in a related field.