L1/L2 Cache Verification Engineer
Description For L1/L2 Cache Verification Engineer
Qualcomm is seeking a Senior L1/L2 Cache Verification Engineer to join their team in Cork, Ireland. This role combines hardware engineering expertise with software verification, focusing on cache microarchitecture and advanced verification methodologies. The position offers an opportunity to work with cutting-edge technology in one of Ireland's major tech hubs.
The role involves developing complex verification environments using UVM methodology, creating sophisticated test benches, and implementing advanced verification strategies. You'll be working with state-of-the-art EDA tools and methodologies including UNR, VSO.AI, and Sim.AI, while collaborating with global teams across architecture, design, and systems.
Cork, as Ireland's second-largest economic center, offers an excellent quality of life and is home to over 170 international companies. The city provides easy access to Europe through its international airport, serving almost 50 destinations. Qualcomm offers a comprehensive benefits package including stock options, performance bonuses, and various insurance coverages, along with strong support for work-life balance through various employee clubs and wellness programs.
The ideal candidate will bring strong expertise in System Verilog/UVM-based verification, cache verification experience, and proficiency in creating complex verification environments. This role represents an excellent opportunity for experienced verification engineers looking to work on cutting-edge semiconductor technology while enjoying the benefits of living in a vibrant European tech hub.
Responsibilities For L1/L2 Cache Verification Engineer
- Gain deep understanding of L2 Cache microarchitecture, including design, features, data paths, block functionalities, and interfaces
- Create complex, constraint-random test benches using UVM methodology
- Develop scalable and reusable test bench components in UVM
- Design and implement comprehensive DV environment
- Collaborate with EDA vendors to explore and implement cutting-edge DV methodologies
- Work closely with architecture, design, and systems teams worldwide
Requirements For L1/L2 Cache Verification Engineer
- Bachelor's degree in computer science, Electrical/Electronic Engineering or related field with 4+ years experience
- Strong System Verilog/UVM based verification skills
- Experience with assertion & coverage-based verification methodology
- Experience in creating complex Cache Verification environment
- Experience in creating complex scoreboard models, checkers in UVM
- Experience with scripting languages such as Perl, Python
Benefits For L1/L2 Cache Verification Engineer
- Salary, stock and performance related bonus
- Maternity/Paternity Leave
- Employee stock purchase scheme
- Matching pension scheme
- Education Assistance
- Relocation and immigration support
- Life, Medical, Income and Travel Insurance
- Subsidised memberships for physical and mental well-being
- Bicycle purchase scheme
- Employee run clubs
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