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Physical Design Engineer

Leading technology innovator that pushes boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation.
$98,500 - $147,700
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
Enterprise SaaS · Hardware

Job Description

Qualcomm Technologies, Inc. is seeking a Physical Design Engineer to join their Digital ASIC Team. This role offers an exciting opportunity to work with cutting-edge technology in chip design and development. As a Physical Design Engineer, you'll be responsible for implementing complex, high-speed, low power designs including GPU, Camera, DDR, Modem, and Audio components.

The position involves working with state-of-the-art tools and technologies, focusing on complete Physical Design Flow and deliveries. You'll be tasked with developing low power implementation methods, customized place and route optimization, and achieving critical area reduction, performance, and power goals. The role requires expertise in various aspects of chip design including floorplanning, power planning, cell placement, clock tree synthesis, and timing optimization.

Qualcomm offers a comprehensive benefits package including competitive base salary ($98,500 - $147,700), annual bonus opportunities, RSU grants, and extensive health and wellness benefits. The company's culture promotes innovation, collaboration, and professional growth, making it an ideal place for engineers looking to work on breakthrough technologies.

The position is based in San Diego, California, at Qualcomm's headquarters, where you'll work alongside industry experts and contribute to projects that shape the future of mobile and wireless technology. This role requires a Bachelor's degree in Science or Engineering and at least 2 years of relevant industry experience, offering an excellent opportunity for career growth in the semiconductor industry.

Last updated 2 months ago

Responsibilities For Physical Design Engineer

  • Innovate, develop, and implement chips and cores using state-of-the-art tools
  • Complete Physical Design Flow and deliveries of complex, high-speed, low power designs
  • Development of low power implementation methods
  • Customized P&R to achieve area reduction, performance, and power goals
  • Floorplanning and power planning
  • IR drop analysis
  • Cell placement
  • Multi-mode & multi-corner clock tree synthesis
  • Routing and timing optimization
  • RC extraction
  • Signal integrity analysis
  • Cross talk noise and delay analysis
  • Debug timing violations and implement fixes
  • Formal verification

Requirements For Physical Design Engineer

Python
Linux
  • Bachelor's degree in Science, Engineering, or related field
  • 2+ years industry experience in Physical Design
  • Experience with Place & Route tools (Cadence Innovus and/or Synopsys Fusion Compiler)
  • Timing closure experience in Synopsys PTSI
  • Formal verification experience
  • Power domain analysis experience
  • Physical verification experience
  • Knowledge of scripting languages (Python, PERL/TCL, Linux/Unix shell and C)

Benefits For Physical Design Engineer

Medical Insurance
401k
Vision Insurance
Dental Insurance
Equity
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health coverage
  • Financial planning support
  • Educational support
  • Wellness programs

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