Physical Design Engineer, Lead
Job Description
Qualcomm, a global leader in technology innovation, is seeking a Lead Physical Design Engineer to join their team in Hyderabad. This role is part of the team responsible for delivering Snapdragon CPU design and flows for high-performance SoCs in sub-10nm process for Mobile, Compute and IOT market space.
The position requires a seasoned professional with at least 7 years of experience in High Performance core Place & Route and ASIC design Implementation. The ideal candidate will work on cutting-edge projects, collaborating with cross-functional teams to develop solutions that push the boundaries of what's possible in mobile and computing technology.
As a Lead Physical Design Engineer, you'll be responsible for crucial aspects of ASIC development, including Place and Route Implementation, Timing Closure, Low Power optimization, and Physical Verification. You'll work closely with RTL design, Synthesis, and various other teams to optimize Performance, Power, and Area (PPA).
The role offers excellent growth opportunities within Qualcomm's innovative environment. The company provides comprehensive benefits including world-class health coverage, financial planning assistance, mental health support, and continuous learning opportunities through tuition reimbursement and mentorship programs.
Qualcomm's commitment to innovation and technological advancement makes this an ideal position for someone looking to work on next-generation mobile and computing solutions. The company's supportive, inclusive culture encourages collaboration and innovation, allowing you to work alongside some of the industry's brightest minds while contributing to world-changing technologies.
This position requires expertise in various tools and technologies, including Place & Route with FC or Innovus, STA using Primetime/Tempus, and programming skills in Perl/Tcl, Python, and C++. The successful candidate will have strong problem-solving abilities and deep understanding of CPU micro-architecture and ASIC development.
Responsibilities For Physical Design Engineer, Lead
- Participate in ASIC development with emphasis in Place and Route Implementation
- Create design experiments and do detailed PPA comparison analysis
- Work with RTL design, Synthesis, low power, Thermal, Power analysis teams
- Develop Place & Route recipes for optimal PPA
- Timing Closure, Low Power, Power Analysis and Physical Verification
- Clock Tree Implementation for High Speed Design
Requirements For Physical Design Engineer, Lead
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 3+ years experience
- 7+ years of High Performance core Place & Route and ASIC design Implementation work experience
- Extensive experience in Place & Route with FC or Innovus
- Experience with STA using Primetime and/or Tempus
- Proficient in constraint generation and validation
- Experience of multiple power domain implementation
- Perl/Tcl, Python, C++ skills
- Strong problem solving and ASIC development/debugging skills
- Experience with CPU micro-architecture
Benefits For Physical Design Engineer, Lead
- World-class health benefit coverage
- Financial future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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