Physical Design Engineer, Staff
Job Description
Qualcomm, a leading technology innovator, is seeking a Staff Physical Design Engineer to join their team in Hyderabad, India. This role represents an exceptional opportunity to work on cutting-edge Snapdragon CPU design and high-performance SoCs in sub-10nm process for Mobile, Compute, and IOT markets.
The position requires a seasoned professional with 9+ years of experience in High Performance core Place & Route and ASIC design Implementation. The ideal candidate will be responsible for crucial aspects of ASIC development, including Place and Route Implementation, Timing Closure, Low Power optimization, Power Analysis, and Physical Verification.
As a Staff Physical Design Engineer, you'll collaborate with cross-functional teams including RTL design, Synthesis, low power, Thermal, and Power analysis teams to optimize Performance, Power, and Area (PPA). The role demands expertise in various technical areas, including Place & Route with FC or Innovus, STA using Primetime/Tempus, and implementation of multiple power domains with complex UPF/CPF definition.
Qualcomm offers an outstanding benefits package, including world-class health coverage, financial planning programs, wellbeing initiatives, and continuous learning opportunities. The company fosters a supportive, inclusive culture where innovative ideas are valued and contribute to world-changing technologies.
The position offers the chance to work alongside leading engineering and technology experts, with access to mentorship programs and professional development opportunities. You'll be part of a team responsible for delivering next-generation technologies that power the mobile, compute, and IoT revolution.
This role is perfect for someone who thrives in a fast-paced environment, has strong problem-solving skills, and is passionate about pushing the boundaries of semiconductor design. You'll have the opportunity to work on projects that directly impact the future of mobile and computing technology while growing your career at a global technology leader.
Responsibilities For Physical Design Engineer, Staff
- Participate in ASIC development with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification
- Create design experiments and conduct PPA comparison analysis
- Work with RTL design, Synthesis, low power, Thermal, Power analysis teams to optimize Performance, Power and Area(PPA)
- Develop Place & Route recipes for optimal PPA
- Tabulate metrics results for analysis comparison
Requirements For Physical Design Engineer, Staff
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering with 4+ years experience or Master's with 3+ years or PhD with 2+ years
- 9+ years of High Performance core Place & Route and ASIC design Implementation work experience
- Extensive experience in Place & Route with FC or Innovus
- Experience with STA using Primetime and/or Tempus
- Experience of multiple power domain implementation with complex UPF/CPF definition
- Perl/Tcl, Python, C++ skills
- Strong problem solving and ASIC development/debugging skills
- Clock Tree Implementation Techniques for High Speed Design Implementation
Benefits For Physical Design Engineer, Staff
- World-class health coverage for employees and eligible dependents
- Financial programs for secure future
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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