Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX, a pioneering space exploration company, is seeking a Senior ASIC Design Engineer to join their Silicon Engineering team in Irvine, CA. This role is crucial for developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures supporting the Starlink satellite constellation, the world's most advanced broadband internet system.

The position offers an opportunity to work alongside world-class cross-disciplinary teams, developing innovative solutions that expand the performance and capabilities of the Starlink network. The role involves sophisticated ASIC design work, from architectural trade-offs to RTL implementation and silicon validation, directly contributing to SpaceX's mission of making reliable internet accessible globally.

As a Sr. ASIC Design Engineer, you'll be responsible for the complete design cycle - from micro-architecture definition to RTL implementation in Verilog/System Verilog, working closely with verification teams and supporting physical implementation. The role requires expertise in complex problem-solving, particularly in areas like clock domain crossings and power optimization.

The position offers competitive compensation ranging from $160,000 to $220,000 annually, complemented by comprehensive benefits including medical coverage, 401(k), stock options, and paid time off. This is an excellent opportunity for experienced ASIC designers who want to contribute to groundbreaking space technology while working for one of the most innovative companies in the aerospace industry.

The ideal candidate will bring 5+ years of RTL implementation experience, strong technical skills in ASIC/SoC system integration, and experience with various EDA tools. The role demands a collaborative mindset, adaptability to a dynamic environment, and willingness to tackle challenging technical problems that directly impact global connectivity infrastructure.