Taro Logo

FPGA Verification Engineer Entry Level Interview Experience - United States

September 14, 2018
Neutral ExperienceNo Offer

Process

The 1st round was an FPGA + Maths HackerRank test. The Maths test had nearly 15 questions, and the FPGA had 15 questions. The FPGA test included:

  • Logic design questions
  • Static timing analysis
  • Finite state machine questions

Questions

Logic Design Questions

Was this helpful?

Interview Statistics

The following metrics were computed from 1 interview experience for the Akuna Capital FPGA Verification Engineer Entry Level role in United States.

Success Rate

0%
Pass Rate

Akuna Capital's interview process for their FPGA Verification Engineer Entry Level roles in the United States is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Akuna Capital's FPGA Verification Engineer Entry Level interview process in United States.

Akuna Capital Work Experiences