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ASIC Design Engineer Interview Experience

July 21, 2018
Positive ExperienceGot Offer

Process

Met with 5 team members on-site after a phone chat with the hiring manager.

Questions covered a variety of topics, including Verilog, C, ASIC design flow, and project experiences.

The interview was not too difficult but covered wide areas.

Questions

Truth table of a simple Verilog module: blocking/unblocking assignments.

Explain LFSR, and what it does.

Metastability and cross-clock domains:

  • Explain setup time and hold time.
  • Explain how a synchronizer works.
  • Explain the 4/2 phase handshake.
  • Explain how an asynchronous FIFO works.

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Interview Statistics

The following metrics were computed from 5 interview experiences for the AMD ASIC Design Engineer role in United States.

Success Rate

40%
Pass Rate

AMD's interview process for their ASIC Design Engineer roles in the United States is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive80%
Neutral20%
Negative0%

Candidates reported having very good feelings for AMD's ASIC Design Engineer interview process in United States.

AMD Work Experiences