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Design Verification Engineer Interview Experience - San Francisco, California

April 1, 2023
Neutral ExperienceNo Offer

Process

The first round consisted of an aptitude test and some technical questions.

This was for a senior position and the interview was conducted by the Manager. The interview lasted for one hour.

Questions

A router transmits the data. If the data is destined for the same address, then the packets should arrive in the same order as they were transmitted. The packet sent second is not allowed to overtake the one sent first. However, if the packets are destined for different addresses, they can overtake other packets. How will you verify this design? The packet does not contain any ID.

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Interview Statistics

The following metrics were computed from 1 interview experience for the AMD Design Verification Engineer role in San Francisco, California.

Success Rate

0%
Pass Rate

AMD's interview process for their Design Verification Engineer roles in San Francisco, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for AMD's Design Verification Engineer interview process in San Francisco, California.

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