Taro Logo

DV Engineer Interview Experience - United States

February 1, 2021
Negative ExperienceGot Offer

Process

C++, array, and queue modeling FSM for pattern detection Depth of the buffer UVM driver example and AXI protocol Scoreboard for out-of-order protocol 8 rounds in total. Swap numbers in a C++ sort array.

Questions

C++: array and queue modeling, FSM for pattern detection

Was this helpful?

Interview Statistics

The following metrics were computed from 1 interview experience for the AMD DV Engineer role in United States.

Success Rate

0%
Pass Rate

AMD's interview process for their DV Engineer roles in the United States is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral0%
Negative100%

Candidates reported having very negative feelings for AMD's DV Engineer interview process in United States.

AMD Work Experiences