I interviewed for the New College grad role.

There was one screening round with the hiring manager (more of a discussion on projects done) and there were 6 rounds of interviews for the panel round.

Screening:

• Setup and hold time violations
• Synthesis constraints (ideal path, false path)
• Open page and closed page policy
• DDR project in-depth

Panel Round: Round 1

• Asynchronous FIFO: How to design and problems faced?
• Synchronous FIFO Verilog code

Round 2

• What is a glitch? When can it occur? Explain with waveforms.
• How to resolve the problem of glitches? How to design glitch-free circuits
• Static and dynamic power, ways to reduce both
• Given a list in Python, sort it without using sort()
• Setup and hold time constraints

Round 3

• Resume projects and experience
• Open page vs. closed page policy
• What is pipelining?
• Adding pipeline registers to the timing path: Its impact on performance and area

Round 4

• Verilog code for a given problem: Given x config(7), y config(6), convert into corresponding x and y coordinates and trace the path (Can be done using FSM for tracing both x and y coordinates).

Round 5

• Verilog coding (Question related to rotating bits for a given number)
• Most challenging problem faced

Round 6

• Verilog arbiter code (3 requests), can store outstanding requests in FIFO.