I recently had an interview with Apple.

I received three phone screens and passed two, choosing one to proceed. The recruiters double-checked several times whether I had ever interviewed with Apple before, as it seemed important to them. I assured them I hadn't.

At one point, I asked why their job description online was dated many months ago. The answer given was that not enough people were applying, so they kept searching.

The interview had seven sessions, each lasting 45 minutes. Some sessions extended beyond 45 minutes when the interviewer felt it was necessary, such as when there was a significant, extra question at the end of the session they wanted to include.

In my opinion, the difficulty level was average, but the intensity was high.

One week after the interview, they called to say my background didn't match.

A lot of topics were covered, including: async FIFO, subtleties in async FIFO timing, Gray code counters, async resets, design tricks, gate and latch timing, timing improvement techniques, writing RTL code to design a block based on a given specification, recursive scripting to solve an issue, linked lists, general domain crossing issues, pipelining, and more. There were also a few IQ testing questions.

After I detected the answers in time, I was requested to implement them in a digital circuit. At the end of a session, one interviewer half-jokingly said, "Welcome to Apple." Another interviewer said a few times that I was doing well. A third interviewer assured me that working there was not as busy as people believed.

Overall, I felt the atmosphere was casual, and the difficulty level was average and comfortable.

BTW, most of the questions were NOT standard ones found online. Instead, they tended to be unique, more complicated, and arising from the personal experience of the interviewers (as they told me during the interview). Fortunately, I had either encountered most of them myself in my past experience or was able to come up with a solution during the interview. Here are a few of them:

• Async FIFO: The time for a write pointer to increment, to be synchronized to the read domain, and to cause the read pointer to increment and synchronize back to the write domain. What is the minimum depth of the FIFO?
• Async FIFO: Timing constraint on the write/read pointer (even though it's a false path) so that it won't be sampled incorrectly in the other domain.
• Async FIFO: Timing issue on the path (false path) from the read pointer, to data selection, to a read domain flop. (This is a question I benefited from the interviewer).
• Async FIFO: How to avoid an extra clock of delay when using a Gray code counter. (My method was to keep another copy using a regular counter. The interviewer said he hadn't thought of this method before.)
• Async reset vs. sync reset. Async reset timing analysis.
• If a FIFO's write cycles are pipelined, how to avoid overflow. (My answer was to use a conservative full signal, which the interviewer agreed with.)
• How to pipeline cycles (using a FIFO) on a bus to achieve a desired behavior.
• How to use a latch to solve a big hold time violation (use a low-open latch).
• Timing path that crosses power domains through a level shifter.
• Write a script to traverse a tree structure. (I used recursion, and the interviewer confirmed that was the method he used too.)
• Given a small RTL design, detect flaws in it. (Reset was missing; a domain-crossing interface needs to ensure the number of pulses is preserved after domain crossing.)
• How to use a FIFO in a tricky way to realize a given function (such as widening the FIFO).
• Use a double pointer in a design to solve a certain challenge. (The interviewer confirmed my answer was what he used.)
• Read a waveform and discover the relation between the input and output signals. (At first, it looked tricky. Then soon I found the relation. It involved edge detection, delaying a few cycles, and XORing.)
• Design a block that has control signals, a few inputs, and expected output behavior (though this task is straightforward once understood, it is time-consuming in the interview and creates pressure. I was reminded I made a few typos in my code.)
• Implement a FIFO whose depth is not a power of 2.
• Sequence detector (only this one is a standard question).
• Elastic buffer, de-skew buffer, re-ordering buffer knowledge (as I had little prior knowledge of them, I had some time during the interview to think about them and interacted with the interviewer. It's all based on common sense).