New graduate role, rejected after 3 remote rounds. WAY too many rounds frankly, it all felt like a huge waste of time.

Not asked about personal projects at all or any behavioral questions. Almost entirely technical besides confirming graduation date and legal information (name, university name, etc.).

Technical questions revolved around SystemVerilog and Logic Design. Recommended resources are ChipVerify and EDA Playground.

Asked about basic logic design elements like:

• pattern detector FSM
• priority encoder
• CDC FIFO
• and also primitives

Computer architecture questions focused on hazards and cache/memory topics like MESI. Also asked logic puzzles stripped straight from Cracking the Design Verification Interview book, literally the first question lol.

I was asked about UVM classes but I stated I did not know. Even though I did not claim to know it, the interviewer seemed disappointed.