Interviewer was friendly and helped out with hints. Interview itself covered a lot of topics - Verilog basics, but also Python and C++. Verilog basics included flip flop, shift registers, etc.
Q. Describe your test plan for a FIFO.
The following metrics were computed from 1 interview experience for the Apple Design Verification Engineer role in India.
Apple's interview process for their Design Verification Engineer roles in India is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Apple's Design Verification Engineer interview process in India.