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Design Verification Engineer Interview Experience - Livorno, Italy

June 1, 2020
Neutral ExperienceNo Offer

Process

Applied through referral in the middle of lockdown in Europe.

Had a first chat with HR, where we went through my CV and my motivations.

After 3 weeks, I got a phone interview. This was in line with the position requirements, featuring many SystemVerilog and UVM questions in a row. There wasn't much time to answer, but they were all quick questions.

After another 3 weeks, I had the 5.5-hour interview. It was online due to Covid-19 and involved 6 interviewers, one after the other. All of them were from different sites than the one I applied for, and each appeared specialized in a particular topic. I was asked questions on UVM and SystemVerilog, but also on algorithms and mixed-signal verification (which were not among the requirements).

The interviewers were quite fast, leaving little time to think through problems. It didn't seem like any of them were happy to be there interviewing me, and only one showed interest in what I had done or wanted to do. The rest were simply asking questions. I understand they work for Apple, but perhaps they could adopt a better approach with applicants.

Questions

45 mins phone interview:

  • Task vs. function
  • Associative arrays
  • Packed vs. unpacked
  • Scoreboard structures
  • `uvm_do
  • Sequencer structure
  • Coverage: code vs. functional
  • Functional cov: module and collector
  • Number of automatic bins for an int
  • Code coverage metrics
  • uvm_object vs. uvm_component
  • Concurrent vs. immediate assertions

5 hrs interview:

  • Reg model in UVM
  • Adapter and predictor
  • Scoreboard structure
  • How to use some of the phases
  • Exercise on how to verify a DUT that gets data from 2 sensors
  • List of quick questions on SystemVerilog
  • How to verify req/ack interfaces, also which assertions
  • How to verify in a mixed-signal environment
  • Find errors in given code (like missing "virtual" in parent/child sequences, or missing "automatic" in for loop with fork join_none)
  • Optimized way to generate Fibonacci's sequence
  • Recursive function to generate a given sequence
  • Shortest path algorithm: given starting point and destination point in a 2D matrix, get the shortest path from one to the other, including some non-valid coordinates
  • What kind of functional coverage I have done, how I've done scoreboards, some other questions about CV experiences

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Interview Statistics

The following metrics were computed from 1 interview experience for the Apple Design Verification Engineer role in Livorno, Italy.

Success Rate

0%
Pass Rate

Apple's interview process for their Design Verification Engineer roles in Livorno, Italy is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Apple's Design Verification Engineer interview process in Livorno, Italy.

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