Applied through referral in the middle of lockdown in Europe.
Had a first chat with HR, where we went through my CV and my motivations.
After 3 weeks, I got a phone interview. This was in line with the position requirements, featuring many SystemVerilog and UVM questions in a row. There wasn't much time to answer, but they were all quick questions.
After another 3 weeks, I had the 5.5-hour interview. It was online due to Covid-19 and involved 6 interviewers, one after the other. All of them were from different sites than the one I applied for, and each appeared specialized in a particular topic. I was asked questions on UVM and SystemVerilog, but also on algorithms and mixed-signal verification (which were not among the requirements).
The interviewers were quite fast, leaving little time to think through problems. It didn't seem like any of them were happy to be there interviewing me, and only one showed interest in what I had done or wanted to do. The rest were simply asking questions. I understand they work for Apple, but perhaps they could adopt a better approach with applicants.
45 mins phone interview:
uvm_object vs. uvm_component5 hrs interview:
The following metrics were computed from 1 interview experience for the Apple Design Verification Engineer role in Livorno, Italy.
Apple's interview process for their Design Verification Engineer roles in Livorno, Italy is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Apple's Design Verification Engineer interview process in Livorno, Italy.