The interview process involved two phone rounds followed by an onsite interview in Portland. I was interviewed by six people who asked about various concepts of design, verification, and algorithms. It was quite challenging, to be fair.

The collective experience of the entire team was close to 100 to 130 years, while I had 3 years of experience.

1. Swap in Verilog

2. Print a 2D matrix spirally, starting from the center.

3. Randomize the size of a 2D matrix or multidimensional array.

4. Fork-join and how to disable forks.

5. Assertions.

6. Reverse a string.

7. How to verify a vending machine.

8. Application of the UVM Barrier class.

9. Divide by 5 state machine and extract a mathematical equation to generate the next state.

10. Write a SystemVerilog test to verify if all clocks on the SoC have been switched off after writing 'b1 to a register.

11. Why do we need UVM agents?

12. How is a UVM scoreboard implemented?

13. Constrain an address to be word accessible, with at least two ways to do it.

14. Test Plan and functional coverage.