It was a basic phone screen with quite a lot of questions to code on for Verilog, SystemVerilog, and UVM. Overall, the nature of the questions was not too difficult, but a lot of emphasis was given on syntax.
UVM TB questions:
The following metrics were computed from 25 interview experiences for the Apple Verification Engineer role in United States.
Apple's interview process for their Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Apple's Verification Engineer interview process in United States.