Chandler office. CPU verification team.

1. Logic design - Gave a Verilog code -> build circuit -> optimize it. FSM design
2. Verification - UVM architecture. How will you debug a processor? Verify interrupts in pipeline
3. C++ : Constructors, memory allocation. Structs and OOP. Gave a detailed code snippet. Asked to debug and find errors (headers, function return type mismatch, command line args, memory alloc, constructor related errors)
4. Architecture - Draw pipeline, MSI, cache size calculation, improve cache performance, virtual memory, aliasing and how to solve, TLB and PT, What to do if some mem addresses are not cacheable in pipeline, hazards, ROB structure and workingKnow everything in detail