There were 5 interviews. The first 3 were screeners essentially over the course of 2-3 weeks. The next 2 were technical and were back-to-back.

Interviews felt a bit rushed. There was a 3rd technical interview that was also scheduled but was cancelled last minute (I was only informed of this during the end of the 2nd technical interview). The reason stated was that the 3rd interviewer was sick. Though, it might also be possible that the first 2 interviewers told the 3rd one to cancel as they made the decision to cut it.

The first technical interviewer jumped into tech questions right away. The first one was a c question which I fumbled on. The remainders were textbook PCIe questions specifically about the PL (unfortunately I never worked with PL). None of the questions were verification focused except for maybe one.

The second interviewer was similar but they did end off with one large DV question which I did answer fully and quickly but I think the decision was already made by that time.

Overall I think the interview should be extremely easy. But for the role I was interviewing for (Principal DV engineer), I was expecting questions related to DV, architecture, flow, etc. instead of random LeetCode and textbook questions.

1. A bunch of textbook questions about the PL (i.e. what is data scrambling, what are framing symbols, etc.).

2. Given a screenshot of a waveform, design a monitor and what kind of checks it would need.

3. How to improve simulation performance?

4. What is an ECRC?

5. In c, given an array, remove duplicate entries from the array.