Unscheduled telephone call: I was not expecting the call and was in the middle of another project. The interview started by asking a technical question about SystemVerilog - write code in your head - image the design. ---- I refuse to recite coding standards. Actually, I refer to book and the internet if I cannot remember a SystemVerilog rule - duh!
How do I design an OVM interface for --- using SystemVerilog?
The following metrics were computed from 7 interview experiences for the Cadence Design Systems Application Engineer role.
Cadence Design Systems's interview process for their Application Engineer roles is very selective, failing most engineers who go through it.
Candidates reported having very good feelings for Cadence Design Systems's Application Engineer interview process.