It was through a referral. After a week the interview was held in online mode. The duration of the interview was 2 hrs. It was quite difficult. The resume should be good.
CMOS like VI characteristics, why NAND is used in fabrication.
STA related questions mainly was numerical, Verilog basic concepts questions, System Verilog, verification.
The following metrics were computed from 2 interview experiences for the Cadence Design Systems Application Engineer Intern role in India.
Cadence Design Systems's interview process for their Application Engineer Intern roles in India is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Cadence Design Systems's Application Engineer Intern interview process in India.