Digital Ic Verification Intern Interview Experience - Nanjing, China
Process
I'm a undergraduate student. After submiting CV on the official website, an HR contacted me by phone. Then she set the interview to just 3 days afterwards. The interviewer is a senior engineering at Cadence, who is very kind.
Questions
Do you familiar with UVM verification method？How's your script writing? (She asked nothing related to semiconductor or Integrated circuits).
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Interview Statistics
The following metrics were computed from 1 interview experience for the Cadence Design Systems Digital Ic Verification Intern role in Nanjing, China.
Success Rate
Cadence Design Systems's interview process for their Digital Ic Verification Intern roles in Nanjing, China is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having mixed feelings for Cadence Design Systems's Digital Ic Verification Intern interview process in Nanjing, China.
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