Decent work-life balance, but pay is uncompetitive
Decent work-life balance, but pay is uncompetitive
Decent work life balance, good for freshers
Not offering competitive salary and RSU, not good for experienced persons
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Cadence Design Systems Interview Experiences
Design Verification Engineer
It was on campus placement. Resume shortlisting was done and then direct interview was scheduled (no written test). There were two rounds of interview of an hour each. Both the rounds were technical and mostly focused on SystemVerilog and verificatio
Design Verification Engineer
The questions were practical starting with digital question on FSMs, counters, ff, latches etc. Then Verilog questions involving codes of blocking and non blocking assignments, questions on delays, regions, fork blocks etc. At last, SV questions we
Design Verification Engineer
Basic SV questions with coding. Too many questions on IP. Good interview with manager and one team. 1 phone round and 1 video coding round. Questions about your experience overall
Design Verification Engineer
Bengaluru, IndiaApril 25, 2025It was on campus placement. Resume shortlisting was done and then direct interview was scheduled (no written test). There were two rounds of interview of an hour each. Both the rounds were technical and mostly focused on SystemVerilog and verificatio
Design Verification Engineer
New Delhi, IndiaJuly 29, 2022The questions were practical starting with digital question on FSMs, counters, ff, latches etc. Then Verilog questions involving codes of blocking and non blocking assignments, questions on delays, regions, fork blocks etc. At last, SV questions we
Design Verification Engineer
United StatesJuly 31, 2021Basic SV questions with coding. Too many questions on IP. Good interview with manager and one team. 1 phone round and 1 video coding round. Questions about your experience overall
