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Working culture is good, there are many things for learning
Everything is good, and no cons are there.
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Cadence Design Systems Interview Experiences
Verification Engineer
It was average 1 interviewer, 7 or 8 panels. Interviewer was friendly and asked what activities did I participate in college. He then asked to write the code to implement a sequence detector and then asked a question about circuit theory.
Verification Engineer
Smooth experience, in-depth questions asked on design, verification, scripting languages, computer architecture, linting, Verilog, SV, UVM etc The interviewers were sweet, there were 3 rounds 2 technical one HR.
Verification Engineer
An online test was conducted followed by a technical interview where technical questions from my resume were asked and an HR round. The final selection was announced after all the processes.
Verification Engineer
New Delhi, IndiaJuly 9, 2017It was average 1 interviewer, 7 or 8 panels. Interviewer was friendly and asked what activities did I participate in college. He then asked to write the code to implement a sequence detector and then asked a question about circuit theory.
Verification Engineer
Bengaluru, IndiaJune 1, 2024Smooth experience, in-depth questions asked on design, verification, scripting languages, computer architecture, linting, Verilog, SV, UVM etc The interviewers were sweet, there were 3 rounds 2 technical one HR.
Verification Engineer
IndiaAugust 21, 2022An online test was conducted followed by a technical interview where technical questions from my resume were asked and an HR round. The final selection was announced after all the processes.
