Interview was good, interviewers were friendly, overall experience was good. Mostly focused on SRAM and System Verilog. In the first round, they only concentrated on the SRAM design project, and the second round was with a team lead as they work mostly with System Verilog. They asked me to implement a problem in System Verilog.
SRAM design and follow-up questions.
The following metrics were computed from 2 interview experiences for the Cisco ASIC Design Engineer role in San Jose, California.
Cisco's interview process for their ASIC Design Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Cisco's ASIC Design Engineer interview process in San Jose, California.