I was asked to talk about myself and my experience. Then, the interviewer asked me some verification questions.
These included SystemVerilog related topics:
And a few UVM related topics:
A packet contains an address and data. The address range is split into 4 regions.
Create a class that will generate 100 packets and cover all possible ranges.
The following metrics were computed from 1 interview experience for the Cisco Senior Design Verification Engineer role in San Jose, California.
Cisco's interview process for their Senior Design Verification Engineer roles in San Jose, California is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Cisco's Senior Design Verification Engineer interview process in San Jose, California.