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Senior Design Verification Engineer Interview Experience - San Jose, California

April 1, 2023
Positive ExperienceGot Offer

Process

I was asked to talk about myself and my experience. Then, the interviewer asked me some verification questions.

These included SystemVerilog related topics:

  • Randomization and constraints
  • Using queues
  • Using assertions

And a few UVM related topics:

  • Using TLMs
  • Connection between sequencer and driver

Questions

A packet contains an address and data. The address range is split into 4 regions.

Create a class that will generate 100 packets and cover all possible ranges.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Cisco Senior Design Verification Engineer role in San Jose, California.

Success Rate

100%
Pass Rate

Cisco's interview process for their Senior Design Verification Engineer roles in San Jose, California is incredibly easy as the vast majority of engineers get an offer after going through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Cisco's Senior Design Verification Engineer interview process in San Jose, California.

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