Applied online with a recommendation from a friend who worked at the company for the same job title.
Got a call from a hiring agency within a week. A representative checked over my credentials and set up an interview with an HPE employee who was a team leader for the position.
I cannot recall, but there may have been a short, very basic interview, less than fifteen minutes, with that HPE senior member.
Proceeded to a half-hour to hour-long interview via Zoom with that team leader.
Firstly, we talked about basic things from my resume, like education, experience, and skills.
Then, I was asked some questions regarding my knowledge of the field, like about Verilog, System Verilog, ASIC, testing methods, and how some abstract programming concepts would apply to FPGA design verification.
The interview was not very technical overall.
How would you describe the difference between ASICs and FPGAs?
The following metrics were computed from 1 interview experience for the Hewlett Packard Enterprise Verification Engineer role in United States.
Hewlett Packard Enterprise's interview process for their Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Hewlett Packard Enterprise's Verification Engineer interview process in United States.