Senior verification engineer
Senior verification engineer
Nice colleagues; nice work-life balance.
Low salary, difficult management, and location
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Infineon Technologies Interview Experiences
Verification Engineer
Campus placements were held at IIIT Hyd.
Verification Engineer
At the beginning, there were some basic questions for Verilog and IC design. They also asked some questions about Python or script programming. They asked some Verilog programming questions.
Verification Engineer
To brief it as a one-line sentence: "Not that tough and not that easy." The first round was a telephonic round, later I was invited for a personal interview, followed by a one-on-one interview. I received the offer letter by mail, and it took some
Verification Engineer
Hyderābād, Telangana, IndiaDecember 1, 2010Campus placements were held at IIIT Hyd.
Verification Engineer
GermanyMay 1, 2015At the beginning, there were some basic questions for Verilog and IC design. They also asked some questions about Python or script programming. They asked some Verilog programming questions.
Verification Engineer
Munich, Bavaria, GermanyFebruary 1, 2014To brief it as a one-line sentence: "Not that tough and not that easy." The first round was a telephonic round, later I was invited for a personal interview, followed by a one-on-one interview. I received the offer letter by mail, and it took some
