The manager contacted me on a Friday and asked me to come in on Monday for a one-on-one interview. There, I was asked about programming and logic design questions in Perl, Unix, and Verilog CMOS. The technical interview lasted for 1 hour and 15 minutes, followed by a behavioral interview. Then, they took me out for lunch. That's how it happened. I am still awaiting the result.
What is a formal verification system?
What is code coverage?
The following metrics were computed from 1 interview experience for the Intel Design Automation Engineer, Intern role in Folsom, California.
Intel's interview process for their Design Automation Engineer, Intern roles in Folsom, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's Design Automation Engineer, Intern interview process in Folsom, California.