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Design Automation Engineer, Intern Interview Experience - Folsom, California

June 1, 2009
Positive ExperienceNo Offer

Process

The manager contacted me on a Friday and asked me to come in on Monday for a one-on-one interview. There, I was asked about programming and logic design questions in Perl, Unix, and Verilog CMOS. The technical interview lasted for 1 hour and 15 minutes, followed by a behavioral interview. Then, they took me out for lunch. That's how it happened. I am still awaiting the result.

Questions

What is a formal verification system?

What is code coverage?

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Design Automation Engineer, Intern role in Folsom, California.

Success Rate

0%
Pass Rate

Intel's interview process for their Design Automation Engineer, Intern roles in Folsom, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Design Automation Engineer, Intern interview process in Folsom, California.

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