The interview was 4 hours long and took place at the Intel offices in Toronto.

I first met the manager, who was young and knowledgeable. He asked about my passions, where I see myself in 5 years, my projects at school, and my experience in previous jobs.

I then met the RTL designer, who described the design and asked some design questions.

Next, I met the verification engineers. They asked about my previous projects and also posed some coding questions.

Finally, I met the back-end designer, who mostly asked behavioral questions and discussed my work and passions.

SystemVerilog syntax questions

Design a clock in Verilog without any existing clock signals

Some flip-flop/latch design questions at clock-domain crossing.