Great work-life balance
Great work-life balance
Work-life balance is great. Health benefits.
Leadership struggles with roadmap and goals
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
The interview was average. It covered basic electronic questions, including Verilog, SystemVerilog (SV), and UVM basics. The HR round was disappointing. There was no clear communication from the company regarding the next steps in the process. They
Design Verification Engineer
Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
Internal Transfer within Intel Two phone/video interviews: * Manager interview * Team member interview Each interview is 90 minutes. Interview details: Discussion about experience relating to pre-silicon verification, specifically test bench
Design Verification Engineer
IndiaOctober 1, 2021The interview was average. It covered basic electronic questions, including Verilog, SystemVerilog (SV), and UVM basics. The HR round was disappointing. There was no clear communication from the company regarding the next steps in the process. They
Design Verification Engineer
Haifa, IsraelJanuary 1, 2022Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
United StatesJuly 1, 2022Internal Transfer within Intel Two phone/video interviews: * Manager interview * Team member interview Each interview is 90 minutes. Interview details: Discussion about experience relating to pre-silicon verification, specifically test bench
