Candidates are shortlisted through resumes. After that, they call me during my free time for the interview.
The interviewer was very polite and easy to talk to. He started by discussing my resume and asked some questions regarding it.
He also asked some verification coding questions and assessed my knowledge of Verilog basics.
Basics of Verilog.
Verification coding questions.
Coding questions in Verilog.
The following metrics were computed from 1 interview experience for the Intel Formal Verification Engineer role in New Delhi, India.
Intel's interview process for their Formal Verification Engineer roles in New Delhi, India is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Intel's Formal Verification Engineer interview process in New Delhi, India.