I received a call from HR.

There was a 1.5-hour phone screening, after which I was invited on-site to Folsom.

The interview process included four rounds and a lunch with the team.

I received the results just two days after the interview.

Phone interview:

• Two projects on resume
• Mealy and Moore machines
• FSM for a given sequence
• Basic cache-related questions
• Setup and hold times, and how to fix them
• SRAM vs. DRAM
• Full SRAM operation
• Unix commands: grep, chmod, chop, chomp, ps

Onsite:

Round 1 - Behavioral:

This round was with an engineer who had 22 years of experience at Intel. He primarily asked about my resume and behavioral questions. He also encouraged me to ask him many questions.

Round 2 - Lunch:

Lunch with eight members of the team. The discussion was casual, covering Folsom, my school, and my work at Intel.

Round 3 - Complete Physical Design:

Starting from the flow, the interviewer asked about every aspect. Topics included:

• Inputs to floorplan
• Whether these inputs being available at the Synthesis stage would be beneficial
• Clock tree synthesis (CTS)
• Why CTS is performed after placement
• Timing questions
• How power structure is decided during floorplanning
• Voltage-delay dependence
• Inverted temperature dependence
• Gate sizing
• CMOS fabrication process and diagram
• CMOS layout

Round 4 - Timing and Verification:

More in-depth timing questions and more difficult scenarios were presented. Topics covered:

• Inverters vs. buffers
• SRAM layout
• Why higher metal layers are used for Vdd and Gnd
• Why resistance is lower for higher metal layers
• SPEF and SAIF formats
• Verification basics
• Reliability verification
• Functional verification

Round 5 - Scripting and C++:

Perl questions were asked. I was given a file and asked to extract specific details using regex. Then, I had to use hashes to perform operations on the extracted data. Basic C++ questions and simple programs were also part of this round.