I applied online.

It took two weeks to hear from them. The process involved two rounds:

• First, an interview with the manager.
• Second, an interview with two technical leads of the team.

(Graduate Student at University of Southern California)

1. Day 1 - Call from manager (30 minutes)

• He was very cool, so it wasn't that hard to deal with him.
• He went through some basic aspects of my resume and then technical questions. Some questions I recall are:
  • Can you explain the basic design flow of a system in FPGA?
  • What kind of FPGA did I use in my project?
  • If you get a new FPGA, what components will you expect in it?
  • Describe the basic hardware setup of an FPGA in your lab.
  • How would you debug a design in FPGA? How can you probe different interconnects in your design?
  • Different components of a test bench. What level of simulations were done before generating the bit file and running the design on FPGA?
  • What is PLI (Programming Language Interface)?
  • Difference between blocking and non-blocking assignments, Fork and Join. Different methods in Verilog (always, initial block). How many times does an initial block get executed?

1. Day 2 - Call from two tech leads of the team (1 hour)

• They also started with my projects on my resume. Some questions I recall are:
  • On what aspects of C have you worked? What is the largest program that you have written in C?
  • What do you think are the basic changes from C to C++?
  • What do you mean by polymorphism in C++?
  • Have you used any code debuggers in your projects?
  • On what aspects of Perl have you worked? Did you build the code from scratch, or was it an incremental development?
  • Basic components of a processor?
  • Why do we use cache in a processor? Difference between write-back and write-through policies?
  • Can you think of a disadvantage of cache?
  • If the goal of a design is to minimize (area, delay, power), can you point out the compromise you would make in each of the following: area and delay, delay and power, power and area?
  • Tell me about a situation you faced in your design experience where tests passed in simulation but synthesis failed.
  • If you have an option to select between schematic and RTL, which would you prefer? Why would you mix schematics and RTL in your design?
  • How would you save power by scaling down Vdd? Will that affect the frequency of operation of your design? What is the compromise you would make here?
  • I used a Bloom filter in one of my projects, so they asked what a Bloom filter is. Why did you choose a Bloom filter when so many other hash functions are available?
  • What do you mean by false positives in hash functions?
  • Explain the design approach of an Inter Convertible FIFO, which could be used as a FIFO or as a Data RAM.