The first round of interviews included two 30-minute interviews.
One interview involved writing Verilog code to find the maximum number from a 256-byte ROM. The second interview required writing Verilog code to swap the lower nibble with the higher nibble from a single bit stream.
There were two interviews, each taking 30 minutes.
One involved writing Verilog code to find the maximum number from a 256-byte ROM.
The second interview required writing Verilog code to swap the lower nibble with the higher nibble from a single bitstream.
The following metrics were computed from 1 interview experience for the Intel Lead Engineer role in Toronto, Ontario.
Intel's interview process for their Lead Engineer roles in Toronto, Ontario is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's Lead Engineer interview process in Toronto, Ontario.