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Pre-Si Verification Engineer Interview Experience - Santa Clara, California

February 1, 2011
Neutral ExperienceNo Offer

Process

I had a phone interview with a verification engineer from Intel in Santa Clara.

The position was with the servers group, so the questions were mostly on computer architecture, including basic cache concepts, multilevel cache, and cache coherence protocols.

He also asked a few questions on pipelining.

He then asked me to explain a few of my projects related to computer architecture. This took up the first 50 minutes.

After that, he started asking me questions on C++, algorithms, data structures, and PERL.

The entire interview lasted for 1 hour and 30 minutes.

Questions

What is MESI?

What is a TLB cache? Why is it used?

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Pre-Si Verification Engineer role in Santa Clara, California.

Success Rate

0%
Pass Rate

Intel's interview process for their Pre-Si Verification Engineer roles in Santa Clara, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Intel's Pre-Si Verification Engineer interview process in Santa Clara, California.

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