Step 1: Phone screening (approximately 35-40 minutes). Questions covered MOSFETs, probability, statistics, and projects on the resume.
Step 2: Invited for on-site interviews (4 tech rounds). Detailed questions focused on logic, semiconductor physics, HDLs, and design.
A week later, I was notified of the offer via email.
Solve given logic circuits. Design a regulator (block diagram). Complete HDL code. Perform HDL synthesis, etc.
The following metrics were computed from 8 interview experiences for the Intel Product Development Engineer role in Folsom, California.
Intel's interview process for their Product Development Engineer roles in Folsom, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Intel's Product Development Engineer interview process in Folsom, California.