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Semiconductor Test Engineer Interview Experience - New York, New York

January 1, 2018
Positive ExperienceNo Offer

Process

I was asked about the CV measurements on a MOS capacitor structure. I was asked to draw the band diagram, calculate the flat-band voltage, and MOS capacitance. The interview lasted for one hour.

Questions

What is the frequency limit of MOS capacitance measurements?

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Interview Statistics

The following metrics were computed from 1 interview experience for the Intel Semiconductor Test Engineer role in New York, New York.

Success Rate

0%
Pass Rate

Intel's interview process for their Semiconductor Test Engineer roles in New York, New York is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Semiconductor Test Engineer interview process in New York, New York.

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