Two rounds of interviews:

First round: This was 1.5 hours long and included three questions, a mix of hardware and algorithm topics. I personally received two hardware questions (about timing analysis and a few logic gate designs) and one algorithm question.

Second round: They arranged another 30-minute interview, this time focused on clock analysis (and did not inform me of the topic in advance).

Third interview: They gave me a debrief of the position.

Q: Design a Mealy and Moore FSM using Verilog to detect the pattern "1101".

Q: How does clock skew affect a circuit, and how do you calculate clock skew?

Q: How do you design an algorithm to arrange an array of integers to form the largest possible integer?