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Validation Engineer Interview Experience - Hillsboro, Oregon

March 1, 2015
Positive ExperienceNo Offer

Process

Four parts:

  1. One about Verilog coding: reading and telling what the code is about, and fixing code.

  2. One about computer architecture: the traditional pipeline processor.

  3. One about algorithms: how would you speed up file I/O and processing?

  4. One about virtual memory and exception handling.

Questions

Can you find a way to shorten the Verilog code?

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Intel Validation Engineer role in Hillsboro, Oregon.

Success Rate

50%
Pass Rate

Intel's interview process for their Validation Engineer roles in Hillsboro, Oregon is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Intel's Validation Engineer interview process in Hillsboro, Oregon.

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