After phone call screening, I attended two rounds of technical interviews.
These interviews were related to projects in depth, covering SystemVerilog (SV) and UVM concepts, followed by an assessment of known protocols.
UVM related
Project related
SV concepts
FIFO full/empty conditions
Fork-join concepts
AXI vs AHB difference
The following metrics were computed from 6 interview experiences for the Intel Verification Engineer role in India.
Intel's interview process for their Verification Engineer roles in India is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Intel's Verification Engineer interview process in India.