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Verification Engineer Interview Experience - India

July 1, 2021
Positive ExperienceGot Offer

Process

After phone call screening, I attended two rounds of technical interviews.

These interviews were related to projects in depth, covering SystemVerilog (SV) and UVM concepts, followed by an assessment of known protocols.

Questions

UVM related

Project related

SV concepts

FIFO full/empty conditions

Fork-join concepts

AXI vs AHB difference

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Interview Statistics

The following metrics were computed from 6 interview experiences for the Intel Verification Engineer role in India.

Success Rate

50%
Pass Rate

Intel's interview process for their Verification Engineer roles in India is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive83%
Neutral17%
Negative0%

Candidates reported having very good feelings for Intel's Verification Engineer interview process in India.

Intel Work Experiences