I had two interviews by phone.

The first round was general.

The second round was an actual technical round.

I was about to go for the last round.

There was no funding, so they had to close this position.

Round 1:

1. What is Functional Verification?

Round 2:

1. What is the difference between Verilog and SystemVerilog?
2. What is the difference between blocking and non-blocking assignments?
3. What is an FSM?
4. Mealy and Moore machines
5. What is the difference between synchronous and asynchronous design?
6. Verification using a test environment
7. UVM testbench
8. Synthesis design model
9. Critical path
10. Setup time and hold time
11. Metastable state

And some more verification-related stuff.