Intel

Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent

You will need good digital system experience, including state machines, logic gates, and programming. The language used is Verilog. Be prepared to discuss your previous projects. You should promote your technical capabilities and demonstrate a posit

First, there were some technical questions, and two technical leaders came to the interview. The questions were not very hard, including some basic ones. The technical leaders paid more attention to the value the interviewee could supply to the compa