Good place, pressured environment
Good place, pressured environment
On general, it's a good place to work and to be, but in good times. A place to advance your career.
The company had stock problems, and the pressure kept rising.
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Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
The interview focused mainly on your previous role at Intel. It included some C++ coding questions and questions on cache coherency. There were also questions on opcode flow from core to target. Overall, it was a heavy technical interview.
Design Verification Engineer
2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours.
Design Verification Engineer
Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
Design Verification Engineer
Atlanta, Georgia, United StatesSeptember 1, 2022The interview focused mainly on your previous role at Intel. It included some C++ coding questions and questions on cache coherency. There were also questions on opcode flow from core to target. Overall, it was a heavy technical interview.
Design Verification Engineer
IndiaJanuary 1, 20222 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours. Mainly focused on application-oriented. 2 technical followed by HR. Each round is 1.30-2 hours.
Design Verification Engineer
United StatesMarch 7, 2022Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
