Good Culture, Slow Execution
Good Culture, Slow Execution
Good work culture, great place to work, great immigration attorneys.
Execution is slower compared to other companies.
Was this helpful?
Intel Interview Questions
Intel Interview Experiences
Design Verification Engineer
Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
Design Verification Engineer
They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
Design Verification Engineer
Haifa, IsraelJanuary 1, 2022Two sets of interviews, each two hours long. Two interviewers at each session. Real SystemVerilog questions, no riddles. Topics include: - How to create a verification plan - How to create a test with a sequence - Random virtual sequencer - Agent
Design Verification Engineer
United StatesMarch 7, 2022Moderate. Easy to crack if you prepare well. You need to have a good understanding of all UVM and SV concepts. Protocol concepts also help. Design knowledge is an added advantage. Please attend with proper preparation.
Design Verification Engineer
Bengaluru, Karnataka, IndiaAugust 1, 2024They asked about my Verilog projects and labs that I took in my coursework, and what I achieved in that lab coursework. The interview went slow. Then questions were on the digital domain. Questions on Verilog and C/C++: * STA * Verilog project
